PCI-E 4-port Gigabit Ethernet Controller Card (Intel Chipset) (x4 slot)

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  • This Next-Gen Gigabit Ethernet network card adds four High-Performance Gigabit Ethernet ports to your server or desktop computer, through one PCI Express slot.
  • Up to 86 pieces of queue receiver to adjust (RSS) in a multiple processor system can minimize the use of the CPU.
  • Support 8 pool of each port (single queue) virtual machine device queue (VMDq).
  • Support the SR-IOV function.
  • Support direct cache access (DCA).
  • Support the Intel l/0V3.0 acceleration technology.
  • TS0 interleaved technique is to reduce the delay.
  • To minimize the equipment l/0 interrupt using MSl and MSl-X.
  • The UDP and TCP and IP checksum partial load.
  • The UDP and TCP send piecewise load(TS0).
  • SCTP receiving and sending a check and partial load.
  • The packet combination of interrupt and timer (packet timer) and absolute-interruption delay timer is to send and receive operation.
  • lntel l350AM4 double integrated MAC+ PHY and SERDES chip controller with high-performance, high-reliability and low power consumption characteristics.
  • Hardware acceleration can be partial load task from the main processor. The controller can be used for partial load TCP/UDP/IP checksum.
  • Server level of reliability, availability and performance characteristics:
    • Link aggregation and load balancing.
    • Relevant switches: 802.3AD (LACP), common Trunking(GEC/FEC).
    • Exchange and NIC non-related.
  • Each port can send and receive eight queues.

Description

  • This Next-Gen Gigabit Ethernet network card adds four High-Performance Gigabit Ethernet ports to your server or desktop computer, through one PCI Express slot.
  • Up to 86 pieces of queue receiver to adjust (RSS) in a multiple processor system can minimize the use of the CPU.
  • Support 8 pool of each port (single queue) virtual machine device queue (VMDq).
  • Support the SR-IOV function.
  • Support direct cache access (DCA).
  • Support the Intel l/0V3.0 acceleration technology.
  • TS0 interleaved technique is to reduce the delay.
  • To minimize the equipment l/0 interrupt using MSl and MSl-X.
  • The UDP and TCP and IP checksum partial load.
  • The UDP and TCP send piecewise load(TS0).
  • SCTP receiving and sending a check and partial load.
  • The packet combination of interrupt and timer (packet timer) and absolute-interruption delay timer is to send and receive operation.
  • lntel l350AM4 double integrated MAC+ PHY and SERDES chip controller with high-performance, high-reliability and low power consumption characteristics.
  • Hardware acceleration can be partial load task from the main processor. The controller can be used for partial load TCP/UDP/IP checksum.
  • Server level of reliability, availability and performance characteristics:
    • Link aggregation and load balancing.
    • Relevant switches: 802.3AD (LACP), common Trunking(GEC/FEC).
    • Exchange and NIC non-related.
  • Each port can send and receive eight queues.

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